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19-0814; Rev 0; 5/07
KIT ATION EVALU BLE AVAILA
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
General Description Features
o Dual-Output, Fixed-Frequency, Core Supply Controller o Separate or Combinable Outputs Detected at Power-Up o Reference Buffer Output for NB Controller o 0.4% VOUT Accuracy Over Line, Load, and Temperature o AMD SVI-Compliant Serial Interface o 7-Bit On-Board DAC: 0 to +1.550V Output Adjust Range o Dynamic Phase Selection Optimizes Active/Sleep Efficiency o Transient Phase Repeat Reduces Output Capacitance o True Out-of-Phase Operation Reduces Input Capacitance o Integrated Boost Switches o Programmable AC and DC Droop o Programmable 100kHz to 1.2MHz Switching Frequency o Accurate Current Balance and Current Limit o Adjustable Slew-Rate Control o Power-Good (PWRGD) and Thermal-Fault (VRHOT) Outputs o System Power-OK (PGD_IN) Input o Drives Large Synchronous-Rectifier MOSFETs o 4V to 26V Battery Input-Voltage Range o Overvoltage, Undervoltage, and Thermal-Fault Protection o Power Sequencing and Timing o Soft-Startup and Soft-Shutdown o < 1A Typical Shutdown Current
MAX17009
The MAX17009 is a 2-phase, step-down interleaved, fixed-frequency controller for AMD's(R) serial VID interface (SVI) CPU core supplies. Power-on detection of the CPU configures the MAX17009 as two independent single-phase regulators for a dual CPU core application, or one high-current, dual-phase, combined-output regulator for a unified core application. A reference buffer output (NBV_BUF) sets the voltage-regulation level for a North Bridge (NB) regulator, completing the total CPU cores and NB power requirements. The MAX17009 is fully AMD SVI compliant. Output voltages are dynamically changed through a 2-wire serial interface, allowing the switching regulator and the reference buffer to be individually programmed to different voltages. A programmable slew-rate controller enables controlled transitions between VID codes, soft-start limits the inrush current, and soft-shutdown brings the output voltage back down to zero without any negative ring. Transient phase repeat improves the response of the fixed-frequency architecture. Independently programmable AC and DC droop and selectable offset improve stability and reduce the total output-capacitance requirement. A thermistor-based temperature sensor allows for a programmable thermal-fault output (VRHOT). The MAX17009 includes thermal-fault protection, undervoltage protection (UVP), and selectable output overvoltage protection (OVP). When any of these protection features detect a fault, the controller shuts down. True differential current sensing improves current limit, load-line accuracy, and current balance when operating in combined mode. The MAX17009 has an adjustable switching frequency, allowing 100kHz to 1.2MHz per-phase operation.
Applications
Mobile AMD SVI Core Supply Multiphase CPU Core Supply Voltage-Positioned, Step-Down Converters Notebook/Desktop Computers
Ordering Information
PART MAX17009GTL+ TEMP RANGE -40C to +105C PINPACKAGE 40 TQFN-EP*, 5mm x 5mm PKG CODE T4055-1
Pin Configuration appears at end of data sheet. AMD is a registered trademark of Advanced Micro Devices, Inc.
+Denotes a lead-free package. *EP = Exposed pad.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
ABSOLUTE MAXIMUM RATINGS
VDD1, VDD2, VCC, VDDIO to GND_............................-0.3V to +6V PWRGD to GND_......................................................-0.3V to +6V FBDC_, FBAC_, PRO to GND_ ...................-0.3V to (VCC + 0.3V) GNDS2, THRM, VRHOT to GND_.............................-0.3V to +6V CSP_, CSN_, ILIM to GND_......................................-0.3V to +6V SVC, SVD, PGD_IN to GND_....................................-0.3V to +6V NBV_BUF, NBSKP to GND_ .......................-0.3V to (VCC + 0.3V) REF, OSC, TIME, OPTION to GND_ ..........-0.3V to (VCC + 0.3V) BST1, BST2 to GND_..............................................-0.3V to +36V BST1 to VDD1..........................................................-0.3V to +30V BST2 to VDD2..........................................................-0.3V to +30V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 .............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 .............................................-0.3V to (VBST2 + 0.3V) DL1 to GND_.............................................-0.3V to (VDD1 + 0.3V) DL2 to GND_.............................................-0.3V to (VDD2 + 0.3V) GNDS1, GNDS_NB to GND_.................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) Multilayer PCB (derate 35.7mW/C above +70C) .....2857mW Single-Layer PCB (derate 22.2mW/C above +70C)..1778mW Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INPUT SUPPLIES VIN Input Voltage Range VCC Undervoltage-Lockout Threshold VCC Power-On Reset Threshold VDDIO Undervoltage-Lockout Threshold Quiescent Supply Current (VCC) Quiescent Supply Currents (VDD1, VDD2) Quiescent Supply Current (VDDIO) Shutdown Supply Current (VCC) Shutdown Supply Currents (VDD1, VDD2) Shutdown Supply Current (VDDIO) Reference Voltage Reference Load Regulation REF Fault Lockout Voltage VREF ICC IDD1, IDD2 IDDIO SHDN = GND SHDN = GND SHDN = GND VCC = 4.5V to 5.5V, no REF load Sourcing: IREF = 0 to 500A Sinking: IREF = 0 to -100A Typical hysteresis = 85mV 1.986 -2 VBIAS VDDIO VUVLO VCC rising 50mV typical hysteresis Falling edge, typical hysteresis = 1.1V, faults cleared and DL_ forced high when VCC falls below this level VDDIO rising 100mV typical hysteresis Skip mode, FBDC_ forced above their regulation points Skip mode, FBDC_ forced above their regulation points 0.7 Drain of external high-side MOSFET VCC, VDD1, VDD2 4 4.5 1.0 4.10 4.25 26 5.5 2.7 4.45 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC
1.8
V
0.8 5 0.01 10 0.01 0.01 0.01 2.000 -0.2 0.21 1.84
0.9 10 1 25 1 1 1 2.014 6.2
V mA A A A A A V mV V
2
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER MAIN SMPS CONTROLLERS DAC codes from 0.8375V to 1.5500V DC Output-Voltage Accuracy (Note 1) DC Load Regulation Line-Regulation Error GNDS_ Input Range VGNDS_ VOUT DAC codes from 0.5000V to 0.8250V DAC codes below 0.4875V Either SMPS, PWM mode, droop disabled, zero to full load Either SMPS, 4V < VIN < 26V Separate mode Separate: VOUT_/VGNDS_, -200mV VGNDS_ +200mV; combined: VOUT/VGNDS1, -200mV VGNDS1 +200mV GNDS2, detection after REFOK, latched, cleared by cycling SHDN IFBDC0_ fOSC DMAX tONMIN SMPS2 starts after SMPS1 During transition RTIME = 143k, SR = 6.25mV/s RTIME = 35.7k to 357k, SR = 25mV/s to 2.5mV/s -10 -15 1 50 180 +10 +15 % mV/S CSP_ = CSN_ ROSC = 143k (fOSC = 300kHz nominal) Switching-Frequency Accuracy Maximum Duty Factor Minimum On-Time SMPS1-to-SMPS2 Phase Shift ROSC = 35.7k (fOSC = 1.2MHz nominal) to 432k (fOSC = 99kHz nominal) -200 -0.4 -4 -10 -0.1 0.03 +200 +0.4 +4 +10 % mV % %/V mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17009
GNDS_ Gain
AGNDS_
0.95
1.00
1.05
V/V
GNDS_ Input Bias Current Combined-Mode Detection Threshold FBDC_ Input Bias Current
IGNDS_
-2 0.7 -3 -5 -7.5 90 92 0.8
+2 0.9 +3 +5 +7.5
A V A % %
175
ns % Degrees
TIME Slew-Rate Accuracy
Startup and shutdown CURRENT LIMIT Current-Limit Threshold Tolerance Zero-Crossing Threshold Idle ModeTM Threshold Tolerance CS_ Input-Leakage Current CS_ Common-Mode Input Range Phase-Disable Threshold VLIMIT VZX VIDLE VCSP_ - VCSN_ = 0.05 x (VREF - VILIM), (VREF - VILM) = 0.2V to 1.0V VGND_ - VLX_, SKIP mode VCSP_ - VCSN_, SKIP mode, 0.15 x VLIMIT CSP_ and CSN_ CSP_ and CSN_ CSP2 -1.5 -0.2 0 3 -3
+3 3 +1.5 +0.2 2 VCC -1 VCC -0.4
mV mV mV A V V
Idle Mode is a trademark of Maxim Integrated Products, Inc.
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DROOP AND CURRENT BALANCE DC Droop Amplifier Transconductance DC Droop and Current-Balance Amplifier Offset AC Droop and Current-Balance Amplifier Transconductance AC Droop and Current-Balance Amplifier Offset No-Load Positive Offset with Offset Enabled Gm(FBDC_) IFBDC_/(VCS_), VFBDC_ = VCSN_ = 1.2V, VCSP_ - VCSN_ = -60mV to +60mV IFBDC_/Gm(FBDC_) IFBAC_/(VCS_), Gm(FBAC_) VFBAC_ = VCSN_ = 1.2V, VCSP_ - VCSN_ = -60mV to +60mV IFBAC_/Gm(FBAC_) Offset enabled, OPTION = REF or GND Measured at FBDC_ with respect to steadystate FBDC_ regulation voltage, 5mV hysteresis (typ), transient phase-repeat enabled, OPTION = OPEN or GND DAC codes from 0.8375V to 1.5500V NBV_BUF Output Voltage Accuracy VNBV_BUF DAC codes from 0.5000V to 0.8250V DAC codes below 0.4875V to 0.0125V NBV_BUF Short-Circuit Current (Sets Slew Rate Together with External Capacitor CNBV_BUF) GNDS_NB Input Range GNDS_NB Gain GNDS_NB Input Bias Current FAULT DETECTION Normal operation Output Overvoltage Trip Threshold VOVP_ Measured at FBDC_, rising edge Output not in regulation after a downward VID transition Minimum OVP threshold 250 1.80 300 1.85 0.8 10 -450 -400 -350 s mV 350 1.90 mV VGNDS_NB AGNDS_NB IGNDS_NB VNBV_BUF/VGNDS_NB, -200mV VGNDS_NB +200mV DAC code set to 1.2V, VNBV_BUF = 0.4V and 2V RTIME = 143k, INBV_BUF = 7.0A RTIME = 35.7k to 357k, INBV_BUF = 28A to 2.8A 0.97 1.00 1.03 mS SYMBOL CONDITIONS MIN TYP MAX UNITS
-1.5
+1.5
mV
0.97
1.00
1.03
mS
-1.5 12.5
+1.5
mV mV
Transient Detection Threshold
-32
-18
mV
NB BUFFER -0.4 -4 -10 -10 -15 -200 0.95 -2 1.00 +0.4 +4 +10 +10 % +15 +200 1.05 +2 mV V/V A % mV
V
Output Overvoltage FaultPropagation Delay Output Undervoltage-Protection Trip Threshold
tOVP VUVP
FBDC_ forced 25mV above trip threshold Measured at FBDC_ with respect to unloaded output voltage
4
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Output Undervoltage FaultPropagation Delay SYMBOL tUVP CONDITIONS FBDC_ forced 25mV below trip threshold Measured at FBDC_ with respect to unloaded output voltage 15mV hysteresis (typ) PWRGD Propagation Delay PWRGD Output Low Voltage PWRGD Leakage Current PWRGD Startup Delay and Transition Blanking Time VRHOT Trip Threshold VRHOT Delay VRHOT Output Low Voltage VRHOT Leakage Current THRM Input Leakage Thermal-Shutdown Threshold GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current Dead Time Internal Boost Diode Switch RON RON(DH_) RON(DL_) IDH_ IDL_ (SOURCE) tDH_DL tDL_DH BST_ - LX_ forced High state (pullup) to 5V Low state (pulldown) DL_, high state DL_, low state DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V 0.9 0.7 0.7 0.25 2.2 2.7 8 15 9 25 20 10 40 35 20 2.0 2.0 2.0 0.6 A A A ns TSHDN Hysteresis = 15C tVRHOT IPWRGD_ tBLANK tPWRGD_ MIN TYP 10 MAX UNITS s
MAX17009
Lower threshold, falling edge (undervoltage)
-350
-300
-250 V
PWRGD Threshold
Upper threshold, rising edge (overvoltage)
+150
+200 10
+250 s 0.4 1 V A s
FBDC_ forced 25mV outside the PWRGD trip thresholds ISINK = 4mA High state, PWRGD forced to 5.5V Measured from the time when FBDC_ reaches the target voltage based on the slew rate set by RTIME Measured at THRM, with respect to VCC, falling edge, 115mV hysteresis (typ) THRM forced 25mV below the VRHOT trip threshold, falling edge ISINK = 4mA High state, VRHOT forced to 5V -100 29.5
20
30 10
30.5
% S
0.4 1 +100 160
V A nA C
IDL_ (SINK) DL_ forced to 2.5V DH_ low to DL_ high DL_ low to DH_ high BST1 to VDD1, BST2 to VDD2; measure with 10mA of current
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5
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SVI Logic Input Current SVI Logic Input Threshold SVC Clock Frequency START Condition Hold Time Repeated START Condition Setup Time STOP Condition Setup Time fSVC tHD,STA tSU,STA tSU,STO A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of SCK signal) to bridge the undefined region of SCL's falling edge 10 160 60 Measured from 10% to 90% of VDDIO Input filters on SVD and SVC suppress noise spikes less than 50ns SHDN, PGD_IN PRO, OPTION SHDN, rising edge, hysteresis = 225mV High Four-Level Input-Logic Levels OPTION Open REF Low High Tri-Level Input-Logic Levels PRO Open Low PGD_IN Logic Input Threshold PGD_IN Low state, ISINK = 3mA NBSKP Logic Output Voltage High state, ISOURCE = 3mA VCC 0.4 0.3 x VDDIO VCC 0.4 3.15 3.85 0.4 0.7 x VDDIO 0.4 V V V -1 -3 0.8 VCC 0.4 3.15 1.65 3.85 2.35 0.4 V 20 40 160 160 160 SYMBOL SVC, SVD SVC, SVD, rising edge, hysteresis = 0.15VDDIO CONDITIONS MIN -1 0.3 x VDDIO TYP MAX +1 0.7 x VDDIO 3.4 UNITS A V MHz ns ns ns
2-WIRE SVI BUS LOGIC INTERFACE
Data Hold
tHD,DAT
70
ns
Data Setup Time SVC Low Period SVC High Period SVC/SVD Rise and Fall Time Pulse Width of Spike Suppression INPUTS AND OUTPUTS Logic Input Current Logic Input Threshold
tSU,DAT tLOW tHIGH tR, tF
ns ns ns ns ns
+1 +3 2.0
A V
6
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted.) (Note 2)
PARAMETER INPUT SUPPLIES VIN Input Voltage Range VCC Undervoltage-Lockout Threshold VDDIO Undervoltage-Lockout Threshold Quiescent Supply Current (VCC) Quiescent Supply Currents (VDD1, VDD2) Quiescent Supply Current (VDDIO) Shutdown Supply Current (VCC) Shutdown Supply Currents (VDD1, VDD2) Shutdown Supply Current (VDDIO) Reference Voltage Reference Load Regulation MAIN SMPS CONTROLLERS DAC codes from 0.8375V to 1.5500V DC Output-Voltage Accuracy (Note 1) GNDS_ Input Range VOUT VGNDS_ AGNDS_ DAC codes from 0.5000V to 0.8250V DAC codes from 0.4875V to 0.0125V Separate mode Separate: VOUT_ /VGNDS_, -200mV VGNDS_ +200mV, Combined: VOUT/VGNDS1, -200mV VGNDS1 +200mV GNDS2, detection after REFOK, latched, cleared by cycling SHDN ROSC = 143k (fOSC = 300kHz nominal) Switching-Frequency Accuracy Maximum Duty Factor Minimum On-Time TIME Slew-Rate Accuracy fOSC DMAX tONMIN During transition RTIME = 143k, SR = 6.25mV/s RTIME = 35.7k to 357k, SR = 25mV/s to 2.5mV/s ROSC = 35.7k (fOSC = 1.2MHz nominal) to 432k (fOSC = 99kHz nominal) -0.6 -6 -15 -200 +0.6 +6 +15 +200 % mV mV VREF ICC IDD1, IDD2 IDDIO SHDN = GND, TA = -40C to +85C SHDN = GND, TA = -40C to +85C TA = -40C to +85C VCC = 4.5V to 5.5V, no REF load Sourcing: IREF = 0 to 500A Sinking: IREF = 0 to -100A 1.98 -2 6.2 VBIAS VDDIO VUVLO VCC rising 50mV typical hysteresis VDDIO rising 100mV typical hysteresis Skip mode, FBDC_ forced above their regulation points Skip mode, FBDC_ forced above their regulation points, TA = -40C to +85C Drain of external high-side MOSFET VCC, VDD1, VDD2 4 4.5 1.0 4.10 0.8 26 5.5 2.7 4.45 0.9 10 1 25 1 1 1 2.02 V V mA A A A A A V mV V SYMBOL CONDITIONS MIN MAX UNITS
MAX17009
GNDS_ Gain
0.95
1.05
V/V
Combined-Mode Detection Threshold
0.7 -7.5 -10 90
0.9 +7.5 +10
V
% %
185 -10 -15 +10 +15
ns %
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7
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted.) (Note 2)
PARAMETER CURRENT LIMIT Current-Limit Threshold Tolerance Idle Mode Threshold Tolerance CS_ Common-Mode Input Range Phase Disable Threshold DROOP AND CURRENT BALANCE DC Droop Amplifier Transconductance DC Droop Amplifier Offset AC Droop and Current-Balance Amplifier Transconductance AC Droop and Current-Balance Amplifier Offset IFBDC_ /(VCS_), Gm(FBDC_) VFBDC_ = VCSN_ = 1.2V, VCSP_ - VCSN_ = -60mV to +60mV IFBDC_ /Gm(FBDC_) IFBAC_ /(VCS_), Gm(FBAC_) VFBAC_ = VCSN_ = 1.2V, VCSP_ - VCSN_ = -60mV to +60mV IFBAC_/Gm(FBAC_) Measured at FBDC_ with respect to steady-state FBDC_ regulation voltage, 5mV hysteresis (typ), transient phase repeat enabled, OPTION = OPEN or GND DAC codes from 0.8375V to 1.5500V NBV_BUF Output-Voltage Accuracy VNBV_BUF DAC codes from 0.5000V to 0.8250V DAC codes from 0.4875V to 0.0125V NBV_BUF Short-Circuit Current (Sets Slew Rate Together with External Capacitor CNBV_BUF) GNDS_NB Input Range GNDS_NB Gain VGNDS_NB VNBV_BUF/VGNDS_NB, AGNDS_NB -200mV VGNDS_NB +200mV RTIME = 143k, DAC code set to INBV_BUF = 7.0A 1.2V, VNBV_BUF RTIME = 35.7k to 357k, = 0.4V and 2V INBV_BUF = 28A to 2.8A 0.97 -1.5 0.97 1.03 +1.5 1.03 mS mV mS VLIMIT VIDLE VCSP_ - VCSN_ = 0.05 x (VREF - VILIM), (VREF - VILM) = 0.2V to 1.0V VCSP_ - VCSN_, SKIP mode, 0.15 x VLIMIT CSP_ and CSN_ CSP2 -3 -1.5 0 3 +3 +1.5 2 VCC 0.4 mV mV V V SYMBOL CONDITIONS MIN MAX UNITS
-1.5
+1.5
mV
Transient-Detection Threshold
-32
-18
mV
NB BUFFER -0.6 -6 -15 -10 -15 -200 0.95 +0.6 +6 +15 +10 % +15 +200 1.05 mV V/V % mV
8
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted.) (Note 2)
PARAMETER FAULT DETECTION Output Overvoltage Trip Threshold Output Undervoltage-Protection Trip Threshold VOVP_ VUVP Measured at FBDC_, rising edge Normal operation 250 -450 350 -350 mV mV SYMBOL CONDITIONS MIN MAX UNITS
MAX17009
Measured at FBDC_ with respect to unloaded output voltage Measured at FBDC_ with respect to unloaded output voltage 15mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage)
-350
-250 V
PWRGD Threshold
+150
+250 0.4 V % V
PWRGD Output Low Voltage VRHOT Trip Threshold VRHOT Output Low Voltage GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance Dead Time Internal Boost Diode Switch RON 2-WIRE SVI BUS LOGIC INTERFACE SVI Logic Input Threshold SVC Clock Frequency START Condition Hold Time Repeated START Condition Setup Time STOP Condition Setup Time fSVC tHD,STA tSU,STA tSU,STO RON(DH_) RON(DL_) tDH_DL tDL_DH
ISINK = 4mA Measured at THRM, with respect to VCC, falling edge, 115mV hysteresis (typ) ISINK = 4mA BST_ - LX_ forced to 5V DL_, high state DL_, low state DH_ low to DL_ high DL_ low to DH_ high BST1 to VDD1, BST2 to VDD2, measured with 10mA of current SVC, SVD, rising edge, hysteresis = 0.15 x VDDIO 0.3 x VDDIO 160 160 160 A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of SCK signal) to bridge the undefined region of SCL's falling edge 10 160 60 Measured from 10% to 90% of VDDIO 15 9 High state (pullup) Low state (pulldown) 29.5
30.5 0.4 2.0 2.0 2.0 0.6 40 40 20
ns
0.7 x VDDIO 3.4
V MHz ns ns ns
Data Hold
tHD,DAT
70
ns
Data Setup Time SVC Low Period SVC High Period SVC/SVD Rise and Fall Time
tSU,DAT tLOW tHIGH tR, tF
ns ns ns 40 ns
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9
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, PRO = OPTION = GNDS_NB = GNDS_ = GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40C to +105C, unless otherwise noted.) (Note 2)
PARAMETER INPUTS AND OUTPUTS Logic Input Threshold SHDN, rising edge, hysteresis = 225mV High Four-Level Input Logic Levels OPTION Open REF Low High Tri-Level Input Logic Levels PRO Open Low PGD_IN Logic Input Threshold PGD_IN 0.3 x VDDIO VCC 0.4 3.15 3.85 0.4 0.7 x VDDIO V V 0.8 VCC 0.4 3.15 1.65 3.85 2.35 0.4 V 2.0 V V SYMBOL CONDITIONS MIN MAX UNITS
Note 1: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error comparator threshold by 50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than the error comparator threshold by 50% of the ripple. Note 2: Specifications to TA = -40C to +105C are guaranteed by design, not production tested.
tHDSTT
tR tCLH
SVC tF
tCLL
SVD VIH VIL
tHDDAT
tSUDAT
tSUSTP
tBF
Figure 1. Timing Definitions Used in the Electrical Characteristics
10
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Typical Operating Characteristics
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2125V)
MAX17009 toc01
MAX17009
2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2125V)
95 90 EFFICIENCY (%) 85 80 75 70 65 60 VIN = 7V VIN = 12V VIN = 20V 0.1 10 LOAD CURRENT (A) 100
MAX17009 toc02
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.2125V, -1.2mV/A DROOP)
MAX17009 toc03
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0.1 1 10 VIN = 7V VIN = 12V VIN = 20V
100
1.25
1.23 OUTPUT VOLTAGE (V)
1.21
1.19
1.17 VIN = 12V 0 5 10 LOAD CURRENT (A) 15 20
1.15
100
LOAD CURRENT (A)
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.2000V, NO DROOP)
MAX17009 toc04
1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.8000V)
MAX17009 toc05
2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.8000V)
95 90 EFFICIENCY (%) 85 80 75 70 65 60 VIN = 7V VIN = 12V VIN = 20V 0.1 10 LOAD CURRENT (A) 100
MAX17009 toc06
1.25
100 95 90 EFFICIENCY (%)
100
1.23 OUTPUT VOLTAGE (V)
1.21
85 80 75 70 VIN = 7V VIN = 12V VIN = 20V 0.1 1 10 100
1.19
1.17 65 1.15 0 5 10 LOAD CURRENT (A) VIN = 12V 15 20 60 LOAD CURRENT (A)
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 0.8000V, -1.2mV/A DROOP)
MAX17009 toc07
1-PHASE SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17009 toc08
MAXIMUM INDUCTOR CURRENT vs. INPUT VOLTAGE
VOUT = 1.2V 27 INDUCTOR CURRENT (A) PEAK CURRENT DC CURRENT
MAX17009 toc09
0.84 0.83 0.82 OUTPUT VOLTAGE (V) 0.81 0.80 0.79 0.78 0.77 0.76 0.75 0.74 0 5 10 LOAD CURRENT (A) VIN = 12V 15
350
29
SWITCHING FREQUENCY (kHz)
300
250
25
200
23
150
VIN = 7V VIN = 12V VIN = 20V 0.1 1 10 100
21
100 20 LOAD CURRENT (A)
19 5 10 15 INPUT VOLTAGE (V) 20 25
______________________________________________________________________________________
11
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
MAXIMUM INDUCTOR CURRENT vs. TEMPERATURE
MAX17009 toc10
CURRENT BALANCE vs. LOAD CURRENT
MAX17009 toc11
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17009 toc12
29 VIN = 12V VOUT = 1.2V 27 INDUCTOR CURRENT (A) PEAK CURRENT DC CURRENT
20 VOUT = 1.2V PER-PHASE CURRENT (A) 15
10
SUPPLY CURRENT (mA)
1
25
10
23
0.1 IIN IDD1 + IDD2 ICC 15 INPUT VOLTAGE (V) 20 25
5 IOUT1 IOUT2
21 VOUT = 1.2V 0.01 0 10 20 30 40 5 10 TOTAL LOAD CURRENT (A)
19 -40 -20 0 20 40 60 80 TEMPERATURE (%)
0
REFERENCE VOLTAGE DISTRIBUTION
MAX17009 toc13
SMPS OUTPUT OFFSET VOLTAGE DISTRIBUTION
MAX17009 toc14
NBV_BUF OFFSET VOLTAGE DISTRIBUTION
SAMPLE SIZE = 150 VDAC_NB = 1.200V
MAX17009 toc15
50
70 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 VOUT1 VOUT2
SAMPLE SIZE = 150
SAMPLE SIZE = 150 VDAC1 = VDAC2 = 1.200V
80
SAMPLE PERCENTAGE (%)
SAMPLE PERCENTAGE (%)
40
60
30
40
20
10
20
0 1.995 1.998 2.000 2.003 2.005 REFERENCE VOLTAGE (mV)
0 -5 -3 -1 1 3 5 OUTPUT OFFSET VOLTAGE (mV)
0 -5 -3 -1 1 3 5 OFFSET VOLTAGE (mV)
FBDC TRANSCONDUCTANCE DISTRIBUTION
MAX17009 toc16
REFERENCE VOLTAGE vs. LOAD CURRENT
MAX17009 toc17
STARTUP WAVEFORMS (HEAVY LOAD)
MAX17009 toc18
50 FBDC1 FBDC2 SAMPLE PERCENTAGE (%) 40
SAMPLE SIZE = 150
2.002
A 0 0 0 B C
REFERENCE VOLTAGE (V)
2.001
30
D E F G
2.000 0 1.999 0 0 0 0 20 40 60 80 100 REF LOAD CURRENT (A) 200s/div A. SHDN, 5V/div E. VOUT2, 0.5V/div B. ILX1, 10A/div F. PWRGD, 5V/div C. VOUT1, 0.5V/div G. VNBV_BUF, 0.5V/div D. ILX2, 10A/div VIN = 12V, VBOOT = 0.8V, ILOAD1 = ILOAD2 = 12A
20
10
0 0.990 0.995 1.000 1.005 1.010 TRANSCONDUCTANCE (mS)
1.998
12
______________________________________________________________________________________
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
STARTUP SEQUENCE WAVEFORMS
MAX17009 toc19
MAX17009
SHUTDOWN WAVEFORMS
MAX17009 toc20
1-PHASE LOAD TRANSIENT (-1.2mV/A DROOP)
MAX17009 toc21
0 0 0
A B C D
3.3V 5V 1.2V 5V
A B C 1.2V A
0 0 0 0
E F G H 400s/div A. SHDN, 5V/div E. PWRGD, 3.3V/div B. VNBV_BUF, 0.5V/div F. PGD_IN, 3.3V/div C. VOUT1, 0.5V/div G. SVC, 2V/div D. VOUT2, 0.5V/div H. SVD, 2V/div VIN = 12V, VBOOT = 1.0V, ILOAD1 = ILOAD2 = 3A
D 1.2V E 1.2V F 3.3V 0 200s/div A. SHDN, 5V/div E. VOUT2, 0.5V/div B. DL1, 10V/div F. VNBV_BUF, 2V/div G. PWRGD, 5V/div C. VOUT1, 0.5V/div D. DL2, 10V/div VIN = 12V, ILOAD1 = ILOAD2 = 3A G
15A B 3A 12V 0 20s/div VIN = 12V ILOAD1 = 3A TO 15A TO 3A C
A. VOUT1, 50mV/div B. ILX1, 10A/div C. LX1, 10V/div
1-PHASE TRANSIENT PHASE REPEAT (-1.2mV/A DROOP)
MAX17009 toc22
1-PHASE LOAD TRANSIENT (NO DROOP)
MAX17009 toc23
1-PHASE TRANSIENT PHASE REPEAT (NO DROOP)
MAX17009 toc24
1.2V
A
1.2V
A
1.2V
A
15A B 3A 12V 0 2s/div VIN = 12V ILOAD1 = 3A TO 15A TO 3A C
15A B 3A 12V 0 20s/div VIN = 12V ILOAD1 = 3A TO 15A TO 3A C
15A B 3A 12V 0 2s/div VIN = 12V ILOAD1 = 3A TO 15A TO 3A C
A. VOUT1, 50mV/div B. ILX1, 10A/div C. LX1, 10V/div
A. VOUT1, 50mV/div B. ILX1, 10A/div C. LX1, 10V/div
A. VOUT1, 50mV/div B. ILX1, 10A/div C. LX1, 10V/div
2-PHASE LOAD TRANSIENT (-1.2mV/A DROOP)
MAX17009 toc25
2-PHASE TRANSIENT PHASE REPEAT (-1.2mV/A DROOP)
MAX17009 toc26
1.2V
A
1.2V
A
15A B 3A 15A 0 20s/div VIN = 12V ILOAD = 6A TO 30A TO 6A C
15A B 3A 15A 0 2s/div VIN = 12V ILOAD = 6A TO 30A TO 6A C
A. VOUT1, 50mV/div B. ILX1, 10A/div C. ILX2, 10A/div
A. VOUT1, 50mV/div B. ILX1, 10A/div C. ILX2, 10A/div
______________________________________________________________________________________
13
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25C, unless otherwise noted.)
DYNAMIC OUTPUT-VOLTAGE TRANSITIONS (LIGHT LOAD)
MAX17009 toc29
1-PHASE OUTPUT OVERLOAD
MAX17009 toc27
1-PHASE OUTPUT OVERVOLTAGE
MAX17009 toc28
3.3V 1.2A
A B
3.3V A 1.2A B 5V 1.2V C
1.3V 0.6V 12V 1.3V
A B C
5V 1.2V
C
D 5V 1.2V 0 200s/div A. PWRGD, 5V/div D. VOUT2, 1V/div B. VOUT1, 1V/div E. DL2, 10V/div C. DL1, 10V/div F. VNBV_BUF, 1V/div VIN = 12V, ILOAD1 = 3A TO 30A, ILOAD2 = 3A E F 5V 1.2V 0 200s/div A. PWRGD, 5V/div D. VOUT2, 1V/div B. VOUT1, 1V/div E. DL2, 10V/div C. DL1, 10V/div F. VNBV_BUF, 1V/div VIN = 12V, ILOAD1 = 50mA, ILOAD2 = 3A
D E F
0.6V 12V 1.3V 0.6V 2.5V 2.5V 100s/div A. VNBV_BUF, 1V/div E. VOUT2, 0.5V/div B. LX1, 20V/div F. SVC, 5V/div C. VOUT1, 0.5V/div G. SVD, 5V/div D. LX2, 20V/div VIN = 12V, VDACS = 1.3V TO 0.6V TO 1.3V, ILOAD1 = ILOAD2 = 3A
D E
F G
DYNAMIC OUTPUT-VOLTAGE TRANSITIONS (HEAVY LOAD)
MAX17009 toc30
PGD_IN FALLING TRANSITIONS
MAX17009 toc31
1.3V 0.6V 12V 1.3V
A B C
1.1V 0.8V 0.8V 1.3V
A B
0.6V 12V 1.3V 0.6V 2.5V 2.5V 100s/div A. VNBV_BUF, 1V/div E. VOUT2, 0.5V/div B. LX1, 20V/div F. SVC, 5V/div C. VOUT1, 0.5V/div G. SVD, 5V/div D. LX2, 20V/div VIN = 12V, VDACS = 1.3V TO 0.6V TO 1.3V, ILOAD1 = ILOAD2 = 10A
C D E 1.1V 12V 12V F G 2.5V 2.5V D E F G 10s/div A. VNBV_BUF, 200mV/div E. LX2, 20V/div B. VOUT1, 200mV/div F. PGD_IN, 5V/div C. VOUT2, 200V/div G. PWRGD, 5V/div D. LX1, 20V/div VIN = 12V, VBOOT = 1.1V, VDAC1 = 0.8V, VDAC2 = 1.3V, VNBV_BUF = 0.8V, ILOAD1 = ILOAD2 = 3A
14
______________________________________________________________________________________
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Pin Description
PIN NAME FUNCTION Open-Drain, Power-Good Output. PWRGD indicates when both SMPSs are in regulation. PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions). After output-voltage transitions, except during power-up and power-down, if FBDC_ is in regulation, then PWRGD is high impedance. During startup, PWRGD is held low an additional 20s after the MAX17009 reaches the startup boot voltage set by the SVC, SVD pins. The MAX17009 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN. PWRGD is forced low in shutdown. When in pulse-skipping mode, the upper PWRGD threshold comparator is blanked during a lower VID transition. The upper PWRGD threshold comparator is reenabled once the output is in regulation (Figure 4). North Bridge Buffered Reference Voltage. This output is connected to the REFIN input of the NB controller (switcher or LDO) to set the NB regulator voltage. The NBV_BUF output current is set by the TIME resistor. The NBV_BUF current and the total output capacitance set the NBV_BUF slew rate: 2 NBV_BUF INBV_BUF = (7A) x (143k / RTIME) NBV_BUF Slew rate = INBV_BUF / CNBV_BUF INBV_BUF is the same during startup, shutdown, and any VID transition. Bypass to GND with a 100pF minimum low-ESR (ceramic) capacitor at the NBV_BUF pin. Shutdown Control Input. Connect high (2V to VCC) for normal operation. Connect to ground to put the IC into its 1A max shutdown state. During startup, the SMPS output voltages and the NBV_BUF voltage are ramped up to the voltage set by the SVC, SVD inputs. The SMPSs start up and shut down at a fixed slew rate of 1mV/s. SVC 3 SHDN 0 0 1 1 SVD 0 1 0 1 BOOT VOLTAGE (VBOOT) (PRO = VCC OR GND) 1.1 1.0 0.9 0.8 BOOT VOLTAGE (VBOOT) (PRO = OPEN) 1.1 1.2 1.0 0.8
MAX17009
1
PWRGD
The MAX17009 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN. 4 REF 2.0V Reference Output. Bypass to GND with a 1F maximum low-ESR (ceramic) capacitor. REF sources up to 500A for external loads. Loading REF degrades output accuracy, according to the REF load-regulation error. Current-Limit Adjust Input. The positive current-limit threshold voltage is precisely 1/20 of the voltage between REF and ILIM over a 0.2V to 1.0V range of V(REF, ILIM). The IMIN minimum current-limit threshold voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage. Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and GND to set the switching frequency (per phase): 6 OSC f OSC = 300kHz x 143k / ROSC
5
ILIM
A 35.7k to 432k corresponds to switching frequencies of 1.2MHz to 100kHz, respectively. Switching-frequency selection is limited by the minimum on-time. See the Switching frequency bullet in the SMPS Design Procedure section.
______________________________________________________________________________________
15
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Pin Description (continued)
PIN NAME FUNCTION Slew-Rate Adjustment Pin. Connect a resistor RTIME from TIME to GND to set the internal slew rate: PWM Slew rate = (6.25mV/s) x (143k / RTIME) NBV_BUF Slew rate = (7A) x (143k / RTIME) / CNBV_BUF where RTIME is between 35.7k and 357k for corresponding slew rates between 25mV/s to 2.5mV/s, respectively, for the SMPSs, and NBV_BUF currents between 28A and 2.8A, respectively, for the NBV_BUF. This slew rate applies to both upward and downward VID transitions, and to the transition from boot mode to VID mode. Downward VID transition slew rate can appear slower because the output transition is not forced by the SMPS. The SMPS slew rate for startup and shutdown is fixed at 1mV/s. The NBV_BUF slew rate is the same during startup, shutdown, and normal VID transitions. 8 9 10 SVC SVD THRM Serial VID Clock. During the power-up sequence and in debug mode, SVC is the MSB of the 2-bit VID DAC. Serial VID Data. During the power-up sequence and in debug mode, SVD is the LSB of the 2-bit VID DAC. Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of VCC) at the desired high temperature. SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2 internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. Connect GNDS2 above 0.9V combined-mode operation (unified core). When operating in combined mode, GNDS1 is used as the remote ground-sense input. Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS2. Connect a resistor RFBDC2 between FBDC2 and the positive side of the feedback remote sense to set the DC steady-state droop based on the voltage-positioning gain requirement: 12 FBDC2 RFBDC2 = RDROOPDC / (RSENSE2 x Gm(FBDC2)) where RDROOPDC is the desired voltage positioning slope and Gm(FBDC2) = 1mS typ. RSENSE2 is the value of the current-sense resistor that is used to provide the (CSP2, CSN2) current-sense voltage. To disable the load-line, short FBDC2 to the positive remote-sense point. FBDC2 is high impedance in shutdown. Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS2. The resistance between this pin and the positive side of the remote-sensed output voltage sets the transient AC droop: RFBAC2 = RDROOPAC / (RSENSE2 x Gm(FBAC2)) where RDROOPAC is the transient (AC) voltage-positioning slope that provides an acceptable tradeoff between stability and load transient response, Gm(FBAC2) and RSENSE2 is the value of the current-sense resistor that is used to provide the (CSP2, CSN2) current-sense voltage. The maximum difference between transient (AC) droop and DC droop should not exceed 80mV at the maximum allowed load current (DC droop is set at the FBDC2 pin). Internally, V(FBDC2 - GNDS2) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC2 GNDS2) goes to the error comparator (fast transient loop). FBAC2 is high impedance in shutdown. 14 15 VDDIO GNDS_NB Note: The AC and DC droop cannot be different by more than 3mV/A. CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at VDDIO. North Bridge Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS_NB internally connects to a transconductance amplifier that fine tunes the NBV_BUF output voltage compensating for voltage drops from the regulator ground to the load ground.
7
TIME
11
GNDS2
13
FBAC2
16
______________________________________________________________________________________
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Pin Description (continued)
PIN 16 NAME CSN2 FUNCTION Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Connect CSP2 to VCC to disable SMPS2. This allows the MAX17009 to operate as a 1-phase regulator. Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1F minimum. A VCC UVLO event that occurs while the IC is functioning is latched, and can only be cleared by cycling VCC power or by toggling SHDN. North Bridge Skip Push-Pull Control Output. When NBSKP is high, the NB switching regulator is set to forced-PWM mode. When NBSKP is low, the NB switching regulator is set to pulse-skipping mode. The NBSKP level is set through the serial interface during normal operation. NBSKP is high in shutdown and during soft-shutdown. NBSKP is high in startup until commanded otherwise. SMPS2 High-Side, Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to phase 2's zero-crossing comparator. Boost Flying-Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between VDD2 and BST2 charges the flying capacitor during the time the low-side FET is on. Supply Voltage Input for the DL2 Driver. VDD2 is also the supply voltage used to internally recharge the BST2 flying capacitor during the off-time of phase 2. Connect VDD2 to the 4.5V to 5.5V system supply voltage. Bypass VDD2 to GND with a 1F or greater ceramic capacitor. SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to VDD2. DL2 is forced low in shutdown. DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip mode after an inductor current zero crossing (GND2 - LX2) is detected. Power Ground for SMPS2. Ground connection for the DL2 driver. Also used as an input to SMPS2's zerocrossing comparator. GND1 and GND2 are internally connected. Power Ground for SMPS1. Ground connection for the DL1 driver. Also used as an input to SMPS1's zerocrossing comparator. GND1 and GND2 are internally connected. SMPS1 Low-Side, Gate-Driver Output. DL1 swings from GND1 to VDD1. DL1 is forced low in shutdown. DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip mode after an inductor current zero crossing (GND1 - LX1) is detected. Supply Voltage Input for the DL1 Driver. VDD1 is also the supply voltage used to internally recharge the BST1 flying capacitor during the off-time of phase 1. Connect VDD1 to the 4.5V to 5.5V system supply voltage. Bypass VDD1 to GND with a 1F or greater ceramic capacitor. Boost Flying-Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between VDD1 and BST1 charges the flying capacitor during the time the low-side FET is on. SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to phase 1's zero-crossing comparator. SMPS1 High-Side, Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below 1.5V (30% of VCC). VRHOT is high impedance in shutdown.
MAX17009
17
CSP2
18
VCC
19
NBSKP
20 21 22
DH2 LX2 BST2
23
VDD2
24
DL2
25 26
GND2 GND1
27
DL1
28
VDD1
29 30 31 32
BST1 LX1 DH1 VRHOT
______________________________________________________________________________________
17
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Pin Description (continued)
PIN NAME FUNCTION Protection Disable. PRO also sets the MAX17009 in debug mode. Connect PRO high to disable OVP protection. Connect PRO to GND to enable OVP protection. When PRO is floated, the MAX17009 disables the OVP protection and also enters debug mode (see the SHDN pin description). When PGD_IN is low in debug mode, the MAX17009 DAC voltages are set by the 2-bit boot VID. When PGD_IN is high, the MAX17009 changes to serial VID mode. Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. System Power-Good Input. Indicates to the MAX17009 that the system is ready to enter serial VID mode. PGD_IN is low when SHDN first goes high, the MAX17009 decodes the boot VID to determine the boot voltage. The boot VID can be changed dynamically while PGD_IN remains low and PWRGD. The boot VID is stored after PWRGD goes high. PGD_IN goes high after the MAX17009 reaches the boot voltage. This indicates that the SVI block is active, and the MAX17009 starts to respond to the serial-interface commands. After PGD_IN has gone high, if at anytime PGD_IN should go low, the MAX17009 regulates to the previously stored boot VID. Four-Level Input to Enable Offset and Transient-Phase Repeat OPTION VCC OPEN REF GND 37 OPTION OFFSET ENABLED 0 0 1 1 TRANSIENT-PHASE REPEAT ENABLED 0 1 0 1
33
PRO
34 35
CSP1 CSN1
36
PGD_IN
When OFFSET is enabled, the MAX17009 enables a fixed +12.5mV offset on each of the SMPS VID codes after PGD_IN goes high. This configuration is intended for applications that implement a loadline. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting the PSI_L bit to zero through the serial interface. When OFFSET is disabled, the intended application has no load-line, and the FBDC_ pins are directly connected to the remote-sense points. Transient phase repeat allows the MAX17009 to reenable the current phase in response to a load transient, even after that phase has finished its on-pulse. Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The resistance between this pin and the positive side of the remote-sensed output voltage sets the transient AC droop: RFBAC1 = RDROOPAC / (RSENSE1 x Gm(FBAC1)) where RDROOPAC is the transient (AC) voltage-positioning slope that PROvides an acceptable tradeoff between stability and load-transient response, Gm(FBAC1) and RSENSE1 is the value of the current-sense resistor that is used to PROvide the (CSP1, CSN1) current-sense voltage. The maximum difference between transient (AC) droop and DC droop should not exceed 80mV at the maximum allowed load current (DC droop is set at the FBDC2 pin). Internally, V(FBDC1 - GNDS1) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC1 - GNDS1) goes to the error comparator (fast-transient loop). FBAC1 is high impedance in shutdown. Note: The AC and DC droop cannot be different by more than 3mV/A.
38
FBAC1
18
______________________________________________________________________________________
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Pin Description (continued)
PIN NAME FUNCTION Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS1. Connect a resistor RFBDC1 between FBDC1 and the positive side of the feedback remote sense to set the DC steadystate droop based on the voltage-positioning gain requirement: 39 FBDC1 RFBDC1 = RDROOPDC / (RSENSE1 x Gm(FBDC1)) where RDROOPDC is the desired voltage-positioning slope and Gm(FBDC1) = 1mS typ. RSENSE1 is the value of the current-sense resistor that is used to PROvide the (CSP1, CSN1) current-sense voltage. To disable the load-line, short FBDC2 to the positive remote-sense point. FBDC1 is high impedance in shutdown. SMPS1 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS1 internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. GNDS1 is the remote ground-sense input in combined-mode operation. Exposed Pad. Connect the exposed backside pad to GND1 and GND2.
MAX17009
40
GNDS1
EP
EP
Table 1 shows the component selection for standard applications and Table 2 lists component suppliers.
Table 1. Component Selection for Standard Applications
COMPONENT MODE Switching Frequency CIN_, Input Capacitor (per Phase) VIN = 7V TO 20V V OUT = 1.0V - 1.3V / 18A PER PHASE Separate, 2-phase mobile (GNDS2 not high) 280kHz (ROSC = 154k ) (2) 10F, 25V Taiyo Yuden TMK432BJ106KM (2) 470F, 2V, 6m , low-ESR capacitor NEC/Tokin PSGD0E477M6 or Panasonic EEFUD0D471L6 (1) Fairchildsemi FDMS8690 (2) Vishay Si7336ADP 3A, 40V Schottky diode Central Semiconductor CMSH3-40 0.45H, 30A, 1.1m power inductor TOKO FDUE1040D-R45M or NEC/Tokin MPC1040LR45 VIN = 4.5V TO 14V V OUT_ = 1.0V - 1.3V / 18A PER PHASE Separate, 2-phase mobile (GNDS2 not high) 600kHz (ROSC = 71.5k ) (2) 10F, 16V Taiyo Yuden TMK432BJ106KM (2) 330F, 2.5V, 6m , low-ESR capacitor Panasonic EEFSD0D331XR (1) International Rectifier IRF7811W (2) Fairchildsemi FDMS8660S None
C OUT_, Output Capacitor (per Phase)
NH_ High-Side MOSFET NL_ Low-Side MOSFET
DL_ Schottky Rectifier
L_ Inductor
0.22H, 25A, 1m power inductor NEC/Tokin MPC0730LR20
Note: Mobile applications should be designed for separate mode operation. Component selection dependent on AMD CPU AC and DC specifications.
______________________________________________________________________________________
19
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Table 2. Component Suppliers
MANUFACTURER AVX BI Technologies Central Semiconductor Fairchild Semiconductor International Rectifier KEMET NEC Tokin Panasonic WEBSITE www.avxcorp.com www.bitechnologies.com www.centralsemi.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokin.com www.panasonic.com MANUFACTURER Pulse Renesas SANYO Siliconix (Vishay) Sumida Taiyo Yuden TDK TOKO WEBSITE www.pulseeng.com www.renesas.com www.secc.co.jp www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com
Standard Application Circuits
The MAX17009 standard application circuit (Figure 2) generates two independent 18A outputs for AMD mobile CPU applications. See Table 1 for component selections. Table 2 lists the component manufacturers.
Detailed Description
The MAX17009 consists of a dual-fixed-frequency PWM controller that generates the supply voltage for two independent CPU cores. A reference buffer output (NBV_BUF) sets the regulation voltage for a separate NB regulator. The CPU cores can be configured as independent outputs, or as a combined output based on the GNDS2 pin strap (GNDS2 pulled to 1.5V - 1.8V, which are the respective voltages for DDR3 and DDR2). Both SMPS outputs and the NB buffer can be programmed to any voltage in the VID table (see Table 4) using the SVI. The CPU is the SVI bus master, while the MAX17009 is the SVI slave. Voltage transitions are commanded by the CPU as a single-step command from one VID code to another. The MAX17009 slews the SMPS outputs at the slew rate programmed by the external RTIME resistor. For the NB buffer, the slew rate is set by the combination of RTIME and the total capacitance on the output of the buffer. By default, the MAX17009 SMPSs are always in pulseskip mode. In separate mode, the PSI_L bit does not change the mode of operation, but removes the +12.5mV offset, if enabled by the OPTION pin. In combined mode, the PSI_L bit removes the +12.5mV offset and switches from 2-phase to 1-phase operation. The NB_SKP output always follows the state of PSI_L for the NB regulator.
+5V Bias Supply (VCC, VDD) The MAX17009 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's main 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. The 5V bias supply powers both the PWM controller and internal gate-drive power, so the maximum current drawn is: IBIAS = ICC + fSWQG = 10mA to 60mA (typ) where ICC is provided in the Electrical Characteristics table, and fSWQG (per phase) is the driver's supply current, as defined in the MOSFET's data sheet. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Switching Frequency (OSC)
Connect a resistor (ROSC) between OSC and GND to set the switching frequency (per phase): fSW = 300kHz x 143k / ROSC A 35.7k to 432k corresponds to switching frequencies of 1.2MHz to 100kHz, respectively. High-frequency (1.2MHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (100kHz) operation offers the best overall efficiency at the expense of component size and board space. Minimum on-time (tON(MIN)) must also be taken into consideration. See the Switching frequency bullet in the SMPS Design Procedure section.
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
28 RVCC 10 18 CVCC 2.2F VCC DH1 ROSC RTIME CREF 0.22F 4 RILIM1 5 ILIM RILIM2 CONNECT TO SYSTEM 1.8V VDDIO SUPPLY SERIAL INPUT 14 8 9 36 3 37 AGND NH2 33 PRO VDDIO SVC SVD PGD_IN SHDN BST2 OPTION DH2 CSP2 CSN1 REF 6 OSC LX1 DL1 GND1 31 30 27 26 NL1 RCSP1 75 RCSN1 10 CSN1 RCSP2 75 CSP2 RCSN2 10 CSN2 DL1 L1 0.45H VDD1 23 VDD2 BST1 29 CVDD1 1F PWR CBST1 0.22F NH1 CVDD2 1F PWR VIN 4.5V TO 28V CIN1 PWR RSENSE1 1m VCORE0/18A COUT1 2 x 470F 6m +5V
7 TIME
AGND
PWR CSP1
CSP1
34 CCSP1 2.2nF 35 CCSN1 1nF AGND 17
CSP1
CSN1
{
CONNECT TO SYSTEM PWROK SIGNAL ENABLE OPTION OFFSET PH-RPT VCC 0 0 OPEN 0 1 REF 1 0 GND 1 1 PRO 3-LEVEL OPTION: VCC = DISABLE OVP OPEN = DEBUG MODE GND = ENABLE OVP +3.3V R6 100k R7 100k
CCSP2 2.2nF CSN2 16 CCSN2 1nF 22 20
AGND CBST2 0.22F CIN2 PWR
VIN 4.5V TO 28V RSENSE2 1m
MAX17009
LX2 DL2 GND2
21 24 25 RFBAC1 1.5k RFBDC1 1.1 NL2 AGND DL2 L2 0.45H
VCORE1/18A COUT2 2 x 470F 6m
AGND
PWR
CSP2
CSN2
1 32 RTHRM VCC RNTC R5 10 C7 1000pF 10
PWRGD VR_HOT THRM
FBAC1 38
FBDC1
39
R1 100 CORE0 SENSE_H C1 4700pF AGND FROM MAX17009 NB CONTROL NB REGULATOR REFIN SKIP AGND VCORE_NB
15
GNDS_NB
FBAC2 13 12
C3 1000pF RFBAC2 1.5k RFBDC2 1.1
R2 100 CORE1 SENSE_H C2 4700pF AGND CORE0 SENSE_L C5 4700pF R3 100 CORE1 SENSE_L C6 4700pF R4 100 POWER GROUND ANALOG GROUND
FBDC2 AGND 19 2 CNBV_BUF AGND EP AGND
TO NB REGULATOR
NB_SKP NBV_BUF GNDS1 40
C4 1000pF
GNDS2
11
AGND
AGND
Figure 2. Standard Application Circuit
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Interleaved Multiphase Operation
The MAX17009 interleaves both phases--resulting in 180 out-of-phase operation that minimizes the input and output filtering requirements, reduces electromagnetic interference (EMI), and improves efficiency. The highside MOSFETs do not turn on simultaneously during normal operation. The instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input-voltage ripple, ESR power loss, and RMS ripple current (see the Input-Capacitor Selection section). Therefore, the controller achieves high performance while minimizing the component count, which reduces cost, saves board space, and lowers component power requirements, making the MAX17009 ideal for high-power, cost-sensitive applications. where the target voltage (VTARGET) is defined in the Nominal Output-Voltage Selection section, and the FBDC amplifier's output current (IFBDC) is determined by each phase's current-sense voltage: IFBDC = Gm(FBDC)VCS where VCS = VCSP - VCSN is the differential currentsense voltage, and G M(FBDC) is typically 1mS as defined in the Electrical Characteristics table. DC droop is typically used together with the +12.5mV offset feature to keep within the DC tolerance window of the application. See the Offset and Transient-Phase Repeat (OPTION) section. The ripple voltage on FBDC must be less than the 18mV (min) transient phase repeat threshold: ILRSENSEGm(FBDC)RFBDC + ILRESR 18mV 18mV RFBDC - RESR - RSENSEGm(FBDC) IL where IL is the inductor ripple current, RESR is the effective output ESR at the remote sense point, RSENSE is the current-sense element, and Gm(FBDC) is 1.03mS (max) as defined in the Electrical Characteristics table. The worst-case inductor ripple occurs at the maximum input voltage and the minimum output-voltage conditions: IL(MAX) = VOUT(MIN) (VIN(MAX) - VOUT(MIN) ) VIN(MAX)fOSCL
Transient-Phase Repeat When a transient occurs, the output-voltage deviation depends on the controller's ability to quickly detect the transient and slew the inductor current. A fixed-frequency controller typically responds only when a clock edge occurs, resulting in a delayed transient response. To minimize this delay time, the MAX17009 includes enhanced transient detection and transient- phaserepeat capabilities. If the controller detects that the output voltage has dropped by 25mV, the transientdetection comparator immediately retriggers the phase that completed its on-time last. The controller triggers the subsequent phases as normal on the appropriate oscillator edges. This effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response.
The OPTION pin setting enables or disables the transient phase-repeat feature. Keep OPTION OPEN or connected to GND to enable transient-phase repeat. Connect OPTION to VCC or REF to disable transientphase repeat. See the Offset and Transient-Phase Repeat (OPTION) section.
To disable voltage positioning, set RFBDC to zero.
Transient Voltage-Positioning Amplifier (AC Droop) The AC droop amplifier's output (FBAC) connects to the remote-sense point of the output through a resistor that sets each phase's AC voltage-positioning gain:
VOUT = VTARGET - RFBACIFBAC where the target voltage (VTARGET) is defined in the Nominal Output-Voltage Selection section, and the FBAC amplifier's output current (IFBAC) is determined by each phase's current-sense voltage: IFBAC = Gm(FBAC)VCS where VCS = VCSP - VCSN is the differential currentsense voltage, and G M(FBAC) is 1.03mS (max), as defined in the Electrical Characteristics table. AC droop is required for stable operation of the MAX17009. A minimum of 1mV/A is recommended. AC droop must not be disabled.
Feedback Adjustment Amplifiers
Steady-State Voltage-Positioning Amplifier (DC Droop) Each of the MAX17009 SMPS controllers includes two transconductance amplifiers--one for steady-state DC droop, and another for AC droop. The amplifiers' inputs are generated by summing their respective current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor's DCR. The DC droop amplifier's output (FBDC) connects to the remote-sense point of the output through a resistor that sets each phase's DC voltage-positioning gain:
VOUT = VTARGET - RFBDCIFBDC
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
The maximum allowable AC droop is limited by the recommended integrator correction range of 100mV and on the DC droop: RFBAC - RFBDC 100mV 1.03mSILOAD(MAX)RSENSE minimum adjustment range of the integrator amplifier to guarantee proper DC output-voltage accuracy. See the Steady State Voltage-Positioning Amplifiers (DC Droop) and the Transient Voltage-Positioning Amplifiers (AC Droop) sections.
MAX17009
2-Wire Serial Interface (SVC, SVD)
The MAX17009 supports the 2-wire, write only, serialinterface bus as defined by the AMD Serial VID Interface Specification. The serial interface is similar to the high-speed 3.4MHz I2C bus, but without the master mode sequence. The bus consists of a clock line (SVC) and a data line (SVD). The CPU is the bus master, and the MAX17009 is the slave. The MAX17009 serial interface works from 100kHz to 3.4MHz. In the AMD mobile application, the bus runs at 3.4MHz. The serial interface is active only after PGD_IN goes high in the startup sequence. The CPU sets the VID voltage of the three internal DACs and the PSI_L bit through the serial interface. During the startup sequence, the SVC and SVD inputs serve an alternate function to set the 2-bit boot VID for all three DACs while PWRGD is low. In debug mode, the SVC and SVD inputs function in the 2-bit VID mode when PGD_IN is low, and in the serial-interface mode when PGD_IN is high.
Differential Remote Sense The MAX17009 controller includes independent differential, remote-sense inputs for each CPU core to eliminate the effects of voltage drops along the PC board (PCB) traces and through the processor's power pins. The feedback-sense (FBDC_) input connects to the voltage-positioning resistor (R FBDC_ ). The groundsense (GNDS_) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the feedback-sense (FBDC_) voltage-positioning resistor (R FBDC_ ), and ground-sense (GNDS_) input directly to the respective CPU core's remote-sense outputs as shown in Figure 2. GNDS2 has a dual function. At power-on, the voltage level on GNDS2 configures the MAX17009 as two independent switching regulators, or one higher current two-phase regulator. Keep GNDS2 low during powerup to configure the MAX17009 in separate mode. Connect GNDS2 to a voltage above 0.8V (typ) for combined-mode operation. In the AMD mobile system, this is automatically done by the CPU that is plugged into the socket that pulls GNDS2 to the VDDIO voltage level. The MAX17009 checks the GNDS2 level at the time when the internal REFOK signal goes high, and latches the operating mode information (separate or combined mode). This latch is cleared by cycling the SHDN pin. Integrator Amplifier An internal integrator amplifier forces the DC average of the FBDC_ voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 3), allowing accurate DC output-voltage regulation regardless of the output-ripple voltage. The integrator amplifier has the ability to shift the output voltage by 100mV (min). The MAX17009 disables the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode. The integrator remains disabled until 20s after the transition is completed (the internal target settles), and the output is in regulation (edge detected on the error comparator). When voltage positioning is disabled (RFBDC_ = 0), the AC droop setting must be less than the 100mV
Nominal Output-Voltage Selection
SMPS Output Voltage The nominal no-load output voltage (V TARGET_ ) for each SMPS is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (V GNDS ) and the offset voltage (V OFFSET ) as defined in the following equation:
VTARGET = VFBDC = VDAC + VGNDS + VOFFSET where VDAC is the selected VID voltage of the SMPS DAC, VGNDS is the ground-sense correction voltage, and V OFFSET is the +12.5mV offset enabled by the OPTION pin, when the PSI_L is set high.
NBV_BUF Output Voltage The nominal output voltage (VTARGET) for the NBV_BUF is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS), as defined in the following equation:
VTARGET = VNBV _ BUF = VDAC + VGNDS _ NB where V DAC_ is the selected VID voltage of the NBV_BUF DAC, and VGNDS_NB_ is the ground-sense correction voltage. The offset voltage (VOFFSET) is not applied to NBV_BUF.
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
SHDN FAULT1 FAULT2 VCC REF VDDIO RUN 0.3 x VCC VRHOT
MAX17009
REF (2.0V)
UVLO
REFOK OFS_EN DEBUG MODE 7-BIT VID SKIP1 DAC1 DACOUT1 PHASE 1 TARGET AND SLEW-RATE BLOCK BLANK1 TARGET1 GNDS1 PWM_ TIME RUN BLANK2 7-BIT VID DAC3 PHASE 2 TARGET AND SLEW-RATE BLOCK TARGET2 A OUT A/B COMBINE 0.8V CCV1 GNDS_NB OSC x2 IMAX_ INEG_ IMIN_ ILIM CURRENT LIMIT CSA_ REF SKIP_ FBDC1 TARGET1 BLANK1 PHASE 1 FAULT BLOCK FAULT1 PGD1 OSCILLATOR CLOCK1 CLOCK2 ISLOPE1 ISLOPE2 CCV1S CCV2S CCV2 PWM_ CSA_ TARGET_ IMAX_ IMIN_ SKIP_ CLOCK_ TPR_EN DRP_EN ISLOPE_ CCV_S CCV_ FBDC2 OPTION 4-LEVEL DECODE OFS_EN TPR_EN TARGET2 BLANK2 PHASE 2 FAULT BLOCK PGD2 FAULT2 PWRGD x2 B GNDS1 GNDS2 SKIP_ DRIVER BLOCK LX_ DL_ GND_ x2 BST_ DH_ THRM VDD
PGD_IN VDDIO SVC SVD
SVI INTERFACE 7-BIT VID SKIP2
DAC2
DACOUT2
SKIP3
NBSKP NBV_BUF TIME
DACOUT3
FBAC_ PWM BLOCK FBDC_
CSN_ CSP_
PRO
3-LEVEL DECODE
PRO DEBUG MODE
Figure 3. Functional Diagram
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
7-Bit DAC Inside the MAX17009 are three 7-bit digital-to-analog converters (DACs). Each DAC can be individually programmed to different voltage levels through the serialinterface bus. The DAC sets the target for the output voltage for the SMPSs and the NB buffer output (NBV_BUF). The available DAC codes and resulting output voltages are compatible with the AMD SVI (Table 4) specifications Boot Voltage On startup, the MAX17009 slews the target for all three DACs from ground to the boot voltage set by the SVC and SVD pin voltage levels. While the output is still below regulation, the SVC and SVD levels can be changed, and the MAX17009 sets the DACs to the new boot voltage. Once the programmed boot voltage is reached and PWRGD goes high, the MAX17009 stores the boot VID. Changes in the SVC and SVD settings do not change the output voltage once the boot VID is stored. When PGD_IN goes high, the MAX17009 exits boot mode, and the three DACs can be independently set to any voltage in the VID table through the serial interface. If PGD_IN goes from high to low anytime after the boot VID is stored, the MAX17009 sets all three DACs back to the voltage of the stored boot VID.
When in debug mode (PRO = OPEN), the MAX17009 uses a different boot-voltage code set. Keeping PGD_IN low allows the SVC and SVD inputs to set the three DACs to different voltages in the boot-voltage code table. When PGD_IN is subsequently set high, the three DACs can be independently set to any voltage in the VID table serial interface. Table 3 shows the bootvoltage code table. The OPTION pin setting enables or disables the +12.5mV offset. Connect OPTION to REF or GND to enable the offset. Keep OPTION open or connected to VCC to disable the offset. See the Offset and TransientPhase Repeat (OPTION) section.
MAX17009
Output-Voltage Transition Timing
SMPS Output-Voltage Transition The MAX17009 performs positive voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. The slew rate (set by resistor RTIME) must be set fast enough to ensure that 35.7k and 357k for corresponding slew rates between 25mV/s to 2.5mV/s, respectively, for the SMPSs.
At the beginning of an output-voltage transition, the MAX17009 blanks both PWRGD comparator thresholds, preventing the PWRGD open-drain output from changing states during the transition. At the end of an upward VID transition, the controller enables both PWRGD thresholds approximately 20s after the slewrate controller reaches the target output voltage. At the end of a downward VID transition, the upper PWRGD threshold is enabled only after the output reaches the lower VID code setting. The MAX17009 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal capacitor and current source programmed by RTIME to transition the output voltage. The total transition time depends on R TIME , the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit set by ILIM. For all dynamic positive VID transitions, the transition time (tTRAN) is given by: t TRAN =
Table 3. Boot-Voltage Code Table
SVC 0 0 1 1 SVD 0 1 0 1 BOOT VOLTAGE (VBOOT) (PRO = VCC OR GND) 1.1 1.0 0.9 0.8 BOOT VOLTAGE (VBOOT) (PRO = OPEN) 1.4 1.2 1.0 0.8
(dVTARGET / dt)
VNEW - VOLD
Offset A +12.5mV offset can be added to both SMPS DAC voltages for applications that include DC droop. The offset is applied only after the MAX17009 exits boot mode (PGD_IN going from low to high), and the MAX17009 enters the serial-interface mode. The offset is disabled when the PSI_L bit is set, saving more power when the load is light.
where dVTARGET/dt = 6.25mV/s x 143k / RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See the TIME Slew-Rate Accuracy row in the Electrical Characteristics table for slew-rate limits. The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current per phase required to make an outputvoltage transition is:
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
IL COUT x (dVTARGET / dt) where dVTARGET/dt is the required slew rate, COUT is the total output capacitance. The MAX17009 SMPSs remain in a pulse-skipping mode even during upward and downward VID transitions. As such, downward VID transitions are not forced, and the output voltage may take a longer time to settle to the lower VID code. The discharge rate of the output voltage during downward transitions is dependent on the load current and total output capacitance for loads less than a minimum current, and dependent on the R TIME programmed slew rate for heavier loads. The critical load current (ILOAD(CRIT)) where the transition time is dependent on the load is: ILOAD(CRIT) COUT x (dVTARGET / dt) For load currents less than ILOAD(CRIT), the transition time is: C x dVTARGET t TRANS OUT ILOAD For soft-start and shutdown, the controller uses a fixed slew rate of 1mV/s. Figure 4 is the VID transition timing diagram. Table 4 shows the output-voltage VID DAC codes.
SVC/SVD
BUS IDLE
BUS IDLE
BUS IDLE
CORE LOAD PWRGD UPPER THRESHOLD CORE VOLTAGE (CORE TARGET) PWRGD LOWER THRESHOLD
LIGHT LOAD UPPER THRESHOLD BLANKED CORE TARGET
HEAVY LOAD
PWRGD
BLANK HIGH IMPEDANCE 20s
BLANK HIGH IMPEDANCE 20s
BLANK HIGH IMPEDANCE 20s
Figure 4. VID Transition Timing Figure
Table 4. Output Voltage VID DAC Codes
SVID[6:0] 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 OUTPUT VOLTAGE (V) 1.5500 1.5375 1.5250 1.5125 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 SVID[6:0] 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 OUTPUT VOLTAGE (V) 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 SVID[6:0] 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 OUTPUT VOLTAGE (V) 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 SVID[6:0] 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 110_1000 110_1001 OUTPUT VOLTAGE (V) 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Table 4. Output Voltage VID DAC Codes (continued)
SVID[6:0] 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 001_1100 001_1101 001_1110 001_1111 OUTPUT VOLTAGE (V) 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 SVID[6:0] 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 011_1101 011_1110 011_1111 OUTPUT VOLTAGE (V) 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 SVID[6:0] 100_1010 100_1011 100_1100 100_1101 100_1110 100_1111 101_0000 101_0001 101_0010 101_0011 101_0100 101_0101 101_0110 101_0111 101_1000 101_1001 101_1010 101_1011 101_1100 101_1101 101_1110 101_1111 OUTPUT VOLTAGE (V) 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 SVID[6:0] 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 111_1101 111_1110 111_1111 OUTPUT VOLTAGE (V) 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0 0 0 0
MAX17009
NBV_BUF Output-Voltage Transition The MAX17009 includes a buffered output voltage that sets the target for the NB regulator. When a voltage transition on the NB DAC occurs, the NBV_BUF sources or sinks a programmed current on its output. The programmed current (INBV_BUF) is set by RTIME. RTIME is between 35.7k and 357k for corresponding INBV_BUF between 28A and 2.8A, respectively: INBV_BUF = (7A) x (143k/ RTIME) INBV_BUF and the external capacitor (CNBV_BUF) set the voltage slew rate of the NBV_BUF: dVNBV_BUF/dt = INBV_BUF / CNBV_BUF Program the NB regulator with a slew rate faster than that set by NBV_BUF to allow the NBV_BUF to control the NB regulator's output slew rate. Alternatively, the NB regulator can be programmed with the desired slew rate, and the NBV_BUF voltage can approach a step function by keeping CNBV_BUF small. A minimum of 100pF capacitor is required.
Pulse-Skipping Operation
The SMPS of the MAX17009 always operates in pulseskipping mode. Pulse-skipping mode enables the driver's zero-crossing comparator, so the driver pulls its DL low when "zero" inductor current is detected (VGND - VLX = 0). This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. In the pulse-skipping operation, the controller terminates the on-time when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the Idle Mode current-sense threshold (VIDLE = 0.15 x VLIMIT). Under heavy-load conditions, the continuous inductor current remains above the Idle Mode current-sense threshold, so the on-time depends only on the feedback-voltage threshold. Under light-load conditions, the controller remains above the feedback voltage threshold, so the on-time duration depends solely on the Idle Mode current-sense threshold, which is approximately 15% of the full-load peak current-limit threshold set by ILIM.
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
During downward VID transitions, the controller temporarily sets the OVP threshold to 1.85V (typ), preventing false OVP faults. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code. The MAX17009 automatically uses forced-PWM operation during soft-shutdown. When configured for separate-mode operation, both SMPSs remain in pulse-skipping mode, regardless of the PSI_L bit state. When configured for combined-mode operation, the PSI_L bit sets the MAX17009 in 1-phase pulse-skipping mode or 2-phase pulse-skipping mode.
MAX17009
inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output-voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).
Current Sense
The output current of each phase is sensed differentially. A low offset voltage and high gain (10V/V) differential current amplifier at each phase allows low-resistance current-sense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage droop-error budget and power monitor. This currentsense method uses an RC filtering network to extract the current information from the output inductor (see Figure 5). The time constant of the RC network should match the inductor's time constant (L/RDCR): L = REQCSENSE RDCR where CSENSE and REQ are the time-constant matching components. To minimize the current-sense error due to the current-sense inputs' bias current (I CSP and ICSN), choose REQ less than 2k and use the above equation to determine the sense capacitance (CSENSE). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage-Positioning and Loop Compensation section for detailed information. When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (LESL) of the current-sense resistor (see Figure 5). The ESL-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. Similar to the inductor DCR sensing method above, the RC filter's time constant should match the L/R time constant formed by the current-sense resistor's parasitic inductance:
Idle Mode Current-Sense Threshold The Idle Mode current-sense threshold forces a lightly loaded regulator to source a minimum amount of power with each on-time since the controller cannot terminate the on-time until the current-sense voltage exceeds the Idle Mode current-sense threshold (V IDLE = 0.15 x VLIMIT). Since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses to avoid overcharging the output. When the clock edge occurs, if the output voltage still exceeds the feedback threshold, the controller does not initiate another on-time. This forces the controller to actually regulate the valley of the output voltage ripple under light-load conditions. Automatic Pulse-Skipping Crossover In skip mode, the MAX17009 zero-crossing comparators are active. Therefore, an inherent automatic switchover to PFM takes place at light loads, resulting in a highly efficient operating mode. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The driver's zero-crossing comparator senses the inductor current across the low-side MOSFET. Once VGND - VLX drops below the zero-crossing threshold, the driver forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the "critical-conduction" point). The load-current level at which the PFM/PWM crossover occurs, ILOAD(SKIP), is given by:
ILOAD(SKIP) = VOUT (VIN - VOUT ) 2VINfSWL
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
INPUT (VIN) CIN NH SENSE RESISTOR L ESL RSENSE COUT
DH_ LX_
MAX17009
DL_
NL
DL
GND CSP_ CSN_ A) SERIES SENSE-RESISTOR SENSING
REQ
CSENSE
INPUT (VIN) CIN NH INDUCTOR LESL RDCR REQ = DL_ NL DL COUT R1 R2 RDCR = GND CSP_ CSN_ B) OUTPUT INDUCTOR DCR SENSING CSENSE FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR. L CSENSE
DH_ LX_
MAX17009
(
R2 R1 + R2
)
RDCR
[
11 + R1 R2
]
Figure 5. Current-Sense Configurations
LESL = REQCSENSE RSENSE where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is current-sense resistance value, and CSENSE and REQ are the time-constant matching components.
current balance between the phases. This control scheme regulates the peak inductor current of each phase, forcing them to remain properly balanced. Therefore, the average inductor current variation depends mainly on the variation in the current-sense element and inductance value.
Combined-Mode Current Balance When configured in combined mode, the MAX17009 current-mode architecture automatically forces the individual phases to remain current balanced. SMPS1 is the main voltage-control loop, and SMPS2 maintains the
Peak Current Limit The MAX17009 current-limit circuit employs a fast peak inductor current-sensing algorithm. Once the currentsense signal (CSP to CSN) of the active phase exceeds the peak current-limit threshold, the PWM controller terminates the on-time. See the Peak-Inductor Current Limit section in the SMPS Design Procedure section.
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Power-Up Sequence (POR, UVLO, PGD_IN)
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC undervoltage lockout (UVLO) circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller--V CC above 4.25V and SHDN driven high. With the reference in regulation, the controller ramps the SMPS and NBV_BUF voltages to the boot voltage set by the SVC and SVD inputs: V t(SMPS-START) = BOOT (1mV / s) t(NBV _ BUF -START) = VBOOTRTIMECNBV _ BUF (7A x 143k) after the SMPS outputs reach regulation. The boot VID is stored the first time PWRGD goes high. The MAX17009 is in pulse-skipping mode during soft-start, and in forced-PWM mode soft-shutdown. The NB regulator soft-start time is set by the NB regulator soft-start timer, or by t(NBV_BUF-START), whichever is longer. For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions and could also result in the stored boot VIDs being corrupted. As such, the MAX17009 immediately stops switching (DH_ and DL_ pulled low), latches off, and discharges the outputs using the internal 10 switches from CSL_ to GND. See Figure 6.
The soft-start circuitry does not use a variable current limit, so full output current is available immediately. PWRGD becomes high impedance approximately 20s
1 DC_IN
2
3
4
5
6
VDDIO
SVC/SVD
2-BIT BOOT VID
SERIAL MODE
BUS IDLE
SHDN
GNDS2 (VDD_PLANE_STRAP)
7
VCORE_ VNBV_BUF 20s PWRGD 10s
BLANK HIGH IMPEDANCE 20s
PGD_IN RESET_L 8
Figure 6. Startup Sequence
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Notes: 1) The relationship between DC_IN and VDDIO is not guaranteed. It is possible to have VDDIO powered when DC_IN is not powered, and it is possible to have DC_IN power-up before VDDIO powers up. 2) As the VDDIO power rail comes within specification, VDD_Plane_Strap becomes valid and SVC and SVD are driven to the boot VID value by the processor. The system guarantees that VDDIO is in specification and SVC and SVD are driven to the boot VID value for at least 10s prior to SHDN being asserted to the MAX17009. 3) After SHDN is asserted, the MAX17009 samples and latches the VDD_Plane_Strap level at its GNDS2 pin when REF reaches the REFOK threshold, and ramps up the voltage-plane outputs to the level indicated by the 2-bit boot VID. The boot VID is stored in the MAX17009 for use when PGD_IN deasserts. The MAX17009 soft-starts the output rails to limit inrush current from the DC_IN rail. 4) The MAX17009 asserts PWRGD. After PWRGD is asserted and all system-wide voltage planes and free-running clocks are within specification, then the system asserts PGD_IN. 5) The processor holds the 2-bit boot VID for at least 10s after PGD_IN is asserted. 6) The processor issues the set VID command through SVI. 7) The MAX17009 transitions the voltage planes to the set VID. The set VID may be greater than, or less than the boot VID voltage. 8) The chipset enforces a 1ms delay between PGD_IN assertion and RESET_L deassertion. PWRGD is forced low during the startup sequence up to 20s after both SMPS internal DACs reach the boot VID. The 2-bit boot VID is stored when PWRGD goes high during the startup sequence. PWRGD is immediately forced low when SHDN goes low. PWRGD is blanked high impedance while either of the internal SMPS DACs are slewing during a VID transition, plus an additional 20s after the DAC transition is completed. For downward VID transitions, the upper threshold of the power-good fault comparators remains blanked until the output reaches regulation again. PWRGD goes low for a minimum of 20s when PGD_IN goes low, and stays low until 20s after both SMPS internal DACs reach the boot VID.
MAX17009
PWRGD The MAX17009 features internal power-good fault comparators for each phase. The outputs of these individual power-good fault comparators are logically ORed to drive the gate of the open-drain PWRGD output transistor. Each phase's power-good fault comparator has an upper threshold of +200mV (typ) and a lower threshold of -300mV (typ). PWRGD goes low if the output of either phase exceeds its respective thresholds.
PGD_IN After the SMPS outputs reach the boot voltage, the MAX17009 switches over to the serial-interface mode when PGD_IN goes high. Anytime during normal operation, a high-to-low transition on PGD_IN causes the MAX17009 to slew all three internal DACs back to the stored boot VIDs. PWRGD goes low for a minimum of 20s when PGD_IN goes low, and stays low until 20s after the SMPS outputs are within the PWRGD thresholds. The SVC and SVD inputs are disabled during the time that PGD_IN is low. The serial interface is reenabled when PGD_IN goes high again. In debug mode (PRO = OPEN), the function of the SVC and SVD inputs depend on the PGD_IN level. If PGD_IN is low, the SVC and SVD inputs are used as 2bit inputs to set the three internal DAC voltages. See Table 3. If PGD_IN is high, the MAX17009 switches over to serial-interface mode. A high-to-low transition on PGD_IN causes the MAX17009 to slew all three internal DACs back to the stored boot VIDs and revert to the 2-bit VID mode. See Figure 7.
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31
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
SVC/SVD BUS IDLE SVC/SVD INPUTS DISABLED BUS IDLE
SVC/SVD (PRO = OPEN)
BUS IDLE
2-BIT BOOT VID
BUS IDLE
VCORE0 (CORE0 TARGET)
(CORE1 TARGET) VCORE1
(NBV_BUF TARGET) VNBV_BUF PGD_IN
PWRGD 20s
BLANK HIGH IMPEDANCE 20s
NOTE: MAX17009 IS IN SKIP MODE. CORE0 IS LIGHTLY LOADED. CORE1 IS HEAVILY LOADED.
Figure 7. PGD_IN Timing Figure
Shutdown
When SHDN goes low, the MAX17009 enters the lowpower shutdown mode. PWRGD is pulled low immediately, and the SMPS output voltages ramp down at 1mV/s, while the NBV_BUF output slews at a rate set by RTIME. At the end of the soft-shutdown sequence, DL_ is kept low, and the 10 switches from CSL_ to GND are enabled, holding the outputs low: t(SMPS-SHDN) = t(NBV _ BUF -SHDN) =
(1mV / s)
VOUT
VNBV _ BUFRTIMECNBV _ BUF (7A x 143k)
Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that
occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. The MAX17009 shuts down completely--the drivers are disabled, the reference turns off, and the supply currents drop to about 1A (max)--20s after the controller reaches the 0V target. When a fault condition--overvoltage or undervoltage--occurs on one SMPS, the other SMPS and the NBV_BUF immediately go through the soft-shutdown sequence. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V. Soft-shutdown for the NB regulator is determined by the particular NB regulator's shutdown behavior. In the typical application, the NB regulator's SHDN pin or enable pin is toggled at the same time as the MAX17009's SHDN pin.
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
VCC RTHRM PLACE RNTC NEXT TO THE HOTTEST POWER COMPONENT. RNTC GND MAX17009 THRM PLACE RPTC1 AND RPTC2 NEXT TO THE RESPECTIVE PHASE'S POWER COMPONENT. RTHRM VCC MAX17009 THRM RPTC1 GND RPTC2
Figure 8. THRM Configuration
VRHOT Temperature Comparator
The MAX17009 features an independent comparator with an accurate threshold (VHOT) that tracks the analog supply voltage (VHOT = 0.3 x VCC). Use a resistorand thermistor-divider between VCC and GND to generate a voltage-regulator overtemperature monitor. Place the thermistor as close to the MOSFETs and inductors as possible. For combined-mode operations, the current-balance circuit balances the currents between phases. As such, the power loss and heat in each phase should be identical, apart from the effects of placement and airflow over each phase. A single thermistor can be placed near either of the phases and still be effective. For separate mode operation, the load currents between phases may be very different. Using two "logic-level" thermistors (e.g., Murata PRF series POSITORS) allows the same VRHOT comparator to monitor the temperature of both phases. Figure 8 is the THRM configuration.
Fault Protection (Latched)
PRO Selectable Overvoltage Protection and Debug Mode The MAX17009 features a tri-level PRO pin that enables the overvoltage protection feature, or puts the MAX17009 in debug mode. Table 5 shows the PRO-selectable options. Debug mode is intended for applications where the serial interface is not properly functioning, and the output voltage needs to be adjusted to different levels. The DAC voltage settings in debug mode further depend on the PGD_IN level to switch between the 2-bit VID setting or the serial interface operation.
Output Overvoltage Protection The overvoltage-protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17009 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV. The OVP threshold tracks the VID DAC voltage except during a downward VID transition. During a downward VID transition, the OVP threshold is set at 1.80V (min), until the output reaches regulation, when the OVP threshold is reset back to 300mV above the VID setting. When the OVP circuit detects an overvoltage fault, it immediately forces the external low-side driver high on the faulted side and initiates the soft-shutdown for the other SMPS and the NBV_BUF. The synchronous-rectifier MOSFETs of the faulted side are turned on with 100% duty, which rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted highside MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. When in combined mode, the synchronous-rectifier MOSFETs of both phases are turned on with 100% duty in response to an overvoltage fault. Overvoltage protection can be disabled by setting PRO to high or open. Output Undervoltage Protection The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX17009 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence for both SMPS and NBV_BUF, and sets the fault latch. Toggle SHDN or cycle the V CC power supply below 0.5V to clear the fault latch and reactivate the controller.
33
Table 5. PRO Settings
PRO VCC OPEN GND DESCRIPTION OVP disabled Debug mode, OVP disabled OVP enabled
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Thermal-Fault Protection The MAX17009 features a thermal-fault protection circuit. When the junction temperature rises above +160C, a thermal sensor sets the fault latch and shuts down, immediately forcing DH and DL low, without going through the soft-shutdown sequence. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C.
C VGS(TH) > VIN RSS CISS Typically, adding a 4700pF between DL and power ground (C NL in Figure 9), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 9). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications where a large VIN - VOUT differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17009 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.25 (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require rising LX edges that do not pull up the low-side MOSFETs' gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET's gate-to-drain capacitance (CRSS), gate-tosource capacitance (C ISS - C RSS ), and additional board parasitics should not exceed the following minimum threshold:
BST
(RBST)* INPUT (VIN) CBST
DH LX
NH L
CBYP VDD
DL (CNL)* PGND
NL
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 9. Gate Drive Circuit
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Table 6. OPTION Pin Settings
OPTION VCC OPEN REF GND OFFSET ENABLED 0 0 1 1 TRANSIENT-PHASE REPEAT ENABLED 0 1 0 1
MAX17009
I ILOAD(PHASE) = LOAD PH where PH is the total number of active phases. * Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. When selecting a switching frequency, the minimum on-time at the highest input voltage and lowest output voltage must be greater than the 185ns (max) minimum on-time specification in the Electrical Characteristics table: VOUT(MIN) / VIN(MAX) x TSW > tONMIN A good rule is to choose a minimum on-time of at least 200ns. When in pulse-skipping operation SKIP_ = GND, the minimum on-time must take into consideration the time needed for proper skip-mode operation. The on-time for a skip pulse must be greater than the 185ns (max) minimum on-time specification in the Electrical Characteristics table: t ONMIN * RSENSE VIN(MAX) - VOUT(MIN)
Offset and Transient-Phase Repeat (OPTION)
The +12.5mV offset and the transient-phase repeat features of the MAX17009 can be selectively enabled and disabled by the OPTION pin setting. Table 6 shows the OPTION pin voltage levels and the features that are enabled. See the Transient Phase Repeat section for a detailed description of the respective features. When the offset is enabled, setting the PSI_L bit low disables the offset reducing power consumption in the lowpower state.
SMPS Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (V IN(MIN) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. * Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase:
(
LVIDLE
)
Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.
Inductor Selection
By design, the AMD Mobile Serial VID application should regard each of the MAX17009 SMPSs as independent, single-phase regulators. The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:
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35
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
VOUT VIN - VOUT L= fSWILOAD(MAX)LIR VIN where ILOAD(MAX) is the maximum current per phase, and fSW is the switching frequency per phase. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. If using a swinging inductor (where the inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (IINDUCTOR) is defined by: IINDUCTOR = VOUT (VIN - VOUT ) VINfSWL
Output-Capacitor Selection
The output filter capacitor must have low-enough ESR to meet output ripple and load-transient requirements. In CPU VCORE converters and other applications where the output is subject to large-load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
(RESR + RPCB ) I
VSTEP
LOAD(MAX)
Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ILOAD(MAX) IINDUCTOR IPEAK = + PH 2
In non-CPU applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are staggered, resulting in lower output-ripple voltage (VRIPPLE) by reducing the total inductor ripple current. For nonoverlapping, multiphase operation (VIN VOUT), the maximum ESR to meet the output-ripple-voltage requirement is: VINfSWL RESR VRIPPLE (VIN - VOUT )VOUT where fSW is the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value (this is true of polymer types). The capacitance value required is determined primarily by the output transient-response requirements. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step. Therefore, the amount of output soar when the load is removed is a function of the output voltage and inductor value. The minimum output capacitance required to prevent overshoot (VSOAR) due to stored inductor energy can be calculated as: COUT
Peak-Inductor Current Limit (ILIM)
The MAX17009 overcurrent protection employs a peak current-sensing algorithm that uses either currentsense resistors or the inductor's DCR as the currentsense element (see the Current Sense section). Since the controller limits the peak inductor current, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input-to-output voltage difference. When combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions. The peak current-limit threshold is set by voltage difference between ILIM and REF using an external resistordivider: VCS(PK) = VCSP_ - VCSN_ = 0.05 x (VREF - VILIM) ILIMIT(PK) = VCS(PK) / RSENSE where RSENSE is the resistance value of the currentsense element (inductors' DCR or current-sense resistor), and ILIMIT(PK) is the desired peak current limit (per phase). The peak current-limit threshold voltage-adjustment range is from 10mV to 50mV.
(ILOAD(MAX) )2L
2VOUT VSOAR
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
When using low-capacity ceramic-filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated.
MAX17009
Input-Capacitor Selection
The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents. For a dual, 180 interleaved controller, the out-of-phase operation reduces the RMS input ripple current, effectively lowering the input capacitance requirements. When both outputs operate with a duty cycle less than 50% (VIN > 2 x VOUT), the RMS input-ripple current is defined by the following equation:
V V IRMS = OUT1 IOUT1(IOUT1 - IIN ) + OUT2 IOUT2 (IOUT2 - IIN ) VIN VIN
where IIN is the average input current: V V IIN = OUT1 IOUT1 + OUT2 IOUT2 VIN VIN In combined mode (GNDS2 = VDDIO) with both phases active, the input RMS current simplifies to: V 1 V IRMS = IOUT OUT - OUT VIN 2 VIN For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX17009 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than 10C temperature rise at the RMS input current for optimal circuit longevity.
Steady-State Voltage Positioning Connect a resistor (RFBDC_) between FBDC_ and the remote-sense point to set the steady-state DC droop (load line) based on the required voltage-positioning slope (RDROOPDC): RFBDC_ = RDROOPDC / (RSENSE_ x Gm(FBDC_)) where RDROOPDC is the desired steady-state droop, Gm(FBDC_) is typically 1ms as defined in the Electrical Characteristics table, and RSENSE_ is the value of the current-sense resistor that is used to provide the (CSP_, CSN_) current-sense voltage. When the inductors' DCR is used as the current-sense element (RSENSE = RDCR), the inductor DCR circuit should include an NTC thermistor to cancel the temperature dependence of the inductor DCR, maintaining a constant voltage-positioning slope. Transient Droop Connect a resistor (RFBAC_) between FBAC_ and the remote-sense point to set the DC transient AC droop (load-line) based on the required voltage-positioning slope (RDROOPAC): RFBAC_ = RDROOPAC / (RSENSE_ x Gm(FBAC_)) where RDROOPAC is the desired steady-state droop, Gm(FBAC_) is typically 1mS as defined in the Electrical Characteristics table, and RSENSE_ is the value of the current-sense resistor that is used to provide the (CSP_, CSN_) current-sense voltage. When the inductors' DCR is used as the current-sense element (RSENSE = RDCR), the inductor DCR circuit should include an NTC thermistor to cancel the temperature dependence of the inductor DCR, maintaining a constant voltage-positioning slope.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V IN(MIN) and V IN(MAX) . Calculate both these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at
37
Voltage Positioning and Loop Compensation
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power-dissipation requirements. The controller uses two transconductance amplifiers to set the transient and DC output-voltage droop (Figure 3). The transient-compensation (TRC) amplifier determines how quickly the MAX17009 responds to the load transient. The FBDC_ amplifier adjusts the steady-state regulation voltage as a function of the load. This adjustability allows flexibility in the
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur (see the MOSFET Gate Drivers section). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low-battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: 2 V I PD(NL Re sistive) = 1 - OUT LOAD RDS(ON) VIN(MAX) TOTAL The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "overdesign" the circuit to tolerate: I ILOAD(MAX) = IPEAK(MAX) - INDUCTOR 2 ILOAD(MAX)LIR = IPEAK(MAX) - 2 where I PEAK(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current per phase. This diode is optional and can be removed if efficiency is not critical.
MAX17009
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: V PD(NHRe sistive) = OUT ILOAD2RDS(ON) VIN where ILOAD is the per-phase current. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: f 2 C PD(NHSwitching) = (VIN(MAX) ) RSS SW ILOAD IGATE where CRSS is the reverse transfer capacitance of NH and IGATE is the peak gate-drive source/sink current (1A typ), and ILOAD is the per-phase current.
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = N x QGATE 200mV
38
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: 2 x 24nC CBST = = 0.24F 200mV Selecting the closest standard value, this example requires a 0.22F ceramic capacitor. The MAX17009 is compatible with the standard SVI interface protocol as defined in the following subsections.
MAX17009
Bus Not Busy The SVI bus is not busy when both data and clock lines remain HIGH. Data transfers can be initiated only when the bus is not busy. Start Data Transfer (S) Starting from an idle bus state (both SVC and SVD are high), a HIGH to LOW transition of the data (SVD) line while the clock (SVC) is HIGH determines a START condition. All commands must be preceded by a START condition. Stop Data Transfer (P) A LOW to HIGH transition of the SDA line while the clock (SVC) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. Figure 10 shows the SVI bus START, STOP, and data change conditions Slave Address After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (110xxxx) for the MAX17009. Since the MAX17009 is a write-only device, the eighth bit of the slave address is zero. The MAX17009 monitors the bus for its corresponding slave address continuously. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. SVD Data Valid The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
SVI Applications Information
I2C-Bus-Compatible Interface
The MAX17009 is a receive-only device. The 2-wire serial bus (pins SVC and SVD) is designed to attach on a low-voltage, I2C-like bus. In the AMD mobile application, the CPU directly drives the bus at a speed of 3.4MHz. The CPU has a push-pull output driving to the VDDIO voltage level. External pullup resistors may be required during the initial power-up sequence before the CPU's push-pull drivers are active. Refer to AMD for specific implementation. When not used in the specific AMD application, the serial interface can be driven to as high as 2.5V, and operate at the lower speeds (100kHz, 400kHz, or 1.7MHz). At lower clock speeds, external pullup resistors can be used for open-drain outputs. Connect both SVC and SVD lines to VDDIO through individual pullup resistors. Calculate the required value of the pullup resistors using: RPULLUP tR CBUS
where tR is the rise time, and should be less than 10% of the clock period. CBUS is the total capacitance on the bus.
SVD
SVC
S START CONDITION DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED
P STOP CONDITION
Figure 10. SVI Bus START, STOP, and Data Change Conditions
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. The device that acknowledges has to pull down the SVD line during the acknowledge clock pulse so the SVD line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. See Figure 11. Figure 12 shows the SVI bus data transfer summary. Command Byte A complete command consists of a START condition (S) followed by the MAX17009's slave address and a data phase, followed by a STOP condition (P).
MAX17009
SMPS Applications Information
Duty-Cycle Limits
Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (tOFF(MIN)). The MAX17009 does not include slope compensation, so the controller becomes unstable with duty cycles greater than 50% per phase: VIN(MIN) 2 x VOUT(MAX) However, the controller can briefly operate with duty cycles over 50% during heavy load transients.
DATA OUTPUT BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE DATA OUTPUT BY MAX17009
ACKNOWLEDGE SVC FROM MASTER 1 S START CONDITION CLK1 2 CLK2 8 CLK8 9 CLK9
ACKNOWLEDGE CLOCK PULSE
Figure 11. SVI Bus Acknowledge
S T A R T
S T O P
S
SLAVE ADDRESS
SET DAC AND PSI_L
P
A C K
A C K
Figure 12. SVI Bus Data Transfer Summary
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Table 7. SVI Send Byte Address Description
BITS 6:4 3 2 Always 110b X = don't care VDAC2, if set, then the following data byte contains the VID for VDAC2; bit 2 is ignored in combined mode (GNDS2 = VDDIO) VDAC1, if set, then the following data byte contains the VID for VDAC1 in separate mode, and the unified VDD in combined mode VDAC_NB, if set then the following data byte contains the VID for VDAC_NB DESCRIPTION
where fSW is the per-phase switching frequency set by the OSC resistor, and tONMIN is 185ns (max) minus the driver's turn-on delay (DL low to DH high). For the best high-voltage performance, use the slowest switching frequency setting (100kHz per phase, ROSC = 432k).
MAX17009
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 13). If possible, mount all the power components on the top side of the board with their ground terminals flush against one another, and mount the controller and analog components on the bottom layer so the internal ground layers shield the analog components from any noise generated by the power components. Follow these guidelines for good PCB layout: * Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. Connect all analog grounds to a separate solid copper plane, then connect the analog ground to the GND pins of the controller. The following sensitive components connect to analog ground: VCC, VDDIO, and REF bypass capacitors, remote-sense and GNDS bypass capacitors, and the resistive connections (ILIM, OSC, TIME). Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. Connections for current limiting (CSP_, CSN_) and voltage positioning (FBS, GNDS) must be made using Kelvin-sense connections to guarantee the current-sense accuracy. Place current-sense filter capacitors and voltage-positioning filter capacitors as close to the IC as possible. Route high-speed switching nodes and driver traces away from sensitive analog areas (REF, VCC, FBAC, FBDC, etc.). Make all pin-strap control input connections (SHDN, PGD_IN, OPTION) to analog ground or VCC rather than power ground or VDD. Route the high-speed serial-interface signals (SVC, SVD) in parallel, keeping the trace lengths identical. Keep the SVC and SVD away from the high-current switching paths.
1
0
Table 8. Serial VID 8-Bit Data Field Encoding
BITS DESCRIPTION PSI_L: Power-Save Indicator: * 0 means the processor is at an optimal load and the regulator(s) can enter power-saving mode. Offset is disabled if previously enabled through the OPTION pin. The MAX17009 enters 1-phase operation if in combined mode (GNDS2 = H). * 1 means the processor is at a high currentconsumption state. Offset is enabled if previously enabled through the OPTION pin. The MAX17009 returns to 2-phase operation if in combined mode (GNDS2 = H). SVID[6:0] as defined in Table 7.
*
7
*
6:0
Maximum Input Voltage The MAX17009 controller has a minimum on-time, which determines the maximum input operating voltage that maintains the selected switching frequency. With higher input voltages, each pulse delivers more energy than the output is sourcing to the load. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, resulting in pulse-skipping operation. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)):
1 VIN(SKIP) = VOUT fSW t ONMIN
*
*
*
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41
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
* Keep the drivers close to the MOSFET, with the gate-drive traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shootthrough currents. When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
VCORE0 VDDNB SPLIT CORE CPU SOCKET
*
VCORE1
COUT COUT KELVIN SENSE VIAS UNDER THE INDUCTORS FOR DCR SENSING
COUT COUT
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and DL anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the driver IC adjacent to the low-side MOSFETs. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the driver IC). 3) Group the gate-drive components (BST capacitors, VDD bypass capacitor) together near the driver IC. 4) Make the DC-DC controller ground connections as shown in the standard application circuit in Figure 2. This diagram can be viewed as having three separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin, VDD bypass capacitor, and driver IC ground connection go; and the controller's analog ground plane where sensitive analog components, the master's GND pin, and VCC bypass capacitor go. The controller's analog ground plane (GND) must meet the power ground plane (PGND) only at a single point directly beneath the IC. The power ground plane should connect to the high-power output ground with a short, thick metal trace from PGND to the source of the low-side MOSFETs (the middle of the star ground). 5) Connect the output power planes (VCORE and system ground planes) directly to the output-filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical. Figure 13 is a PCB layout example.
INDUCTOR
INDUCTOR
CIN CIN
POWER GROUND
CIN CIN
INPUT
CVDD1
CVDD2
CVCC
CONNECT THE EXPOSED PAD TO ANALOG GND ANALOG GROUND (INNER LAYER) CREF
Figure 13. PCB Layout Example
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AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Pin Configuration
GND1 BST1 GND2 BST2 VDD1 VDD2 DL1 LX1 DL2
Chip Information
TRANSISTOR COUNT: 14,497 PROCESS: BiCMOS
MAX17009
TOP VIEW
30 29 28 27 26 25 24 23 22 21 DH1 31 VRHOT 32 PRO 33 CSP1 34 CSN1 35 PGD_IN 36 OPTION 37 FBAC1 38 FBDC1 39 GNDS1 40 1 PWRGD 2 NBV_BUF 3 SHDN 4 REF 5 ILIM 6 OSC 7 TIME 8 SVC 9 SVD 10 THRM 20 DH2 19 NBSKP 18 VCC 17 CSP2 16 CSN2
MAX17009
LX2 15 GNDS_NB 14 VDDIO 13 FBAC2 12 FBDC2 11 GNDS2
THIN QFN 5mm x 5mm
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43
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller MAX17009
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
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QFN THIN.EPS
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX17009
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 45
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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